The present invention relates to a pipeline control system for a computer which repetitively reuses the contents of a second stage tag register while the next instructions are being read and loaded into an alternate second stage tag register.
In general, when an electronic computer is controlled using a pipeline control method, instructions 1 through 13 successively pass through processing stages I through VI according to a timing as determined by reference clock cycles t0, t1, t2, . . . , t13, as illustrated in FIG. 1. For example, in processing stage I, an instruction is read-out during processing cycles Ia, Ib1 and Ib2. In processing stage II, an instruction is decoded during processing cycles D and R and a microinstruction is produced. In processing stage III an operand is read out during processing cycles A, B1 and B2. In stage IV, an operation dictated by the decoded instruction is executed during processing cycles E1, E2 and E2D. In the stage V, the result of the operation is checked for branching control, etc., during a processing cycle CK. In the processing stage VI, the result of the operation is stored in general purpose registers during a processing cycle W.
In a pipeline control system as illustrated in FIG. 2, a processing flow is formed of a series of processing cycles consisting of cycle D, for decoding, cycle R, for reading, a cycle A, for address calculation, cycles B1 and B2, for operand read-out, cycles E1 and E2, for operation execution, cycle CK, for result checking, and cycle W result storage. These processing cycles are divided into phases and executed by a known pipeline processing unit PP. Namely, the cycles D and R are included in phase-1, the cycles A and B1 are included in phase 2, the cycles B2 and E1 are included in phase-3, the cycle E2 is included in phase-4, the cycle CK is included in phase-5, and the cycle W is included in phase-6. The processing flow is controlled by an instruction register INS REG, control storage CS, tag register of phase-1 PH.1 TAG, tag register of phase-2 PH.2 TAG, tag register of phase-3 PH.3 TAG, tag register of phase-4 PH.4 TAG, and tag register of phase-5 PH.5 TAG.
Tag data or execution control information (a microprogram instruction) that is necessary for executing the instructions stored in the instruction register are stored in the control storage CS. When instructions are to be executed, the tag data is successively or sequentially read out from the control storage CS in dependence upon the data in the instruction register INS REG, and supplied successively to the group of tag registers PH.1 TAG, PH.2 TAG, PH.3 TAG, PH.4 TAG and PH 5 TAG. When one instruction is switched to another instruction after a repeated execution instruction is finished, that is, a new instruction is to be executed, a procedure is required to withdraw or cancel the previously employed tag data and to introduce or fetch new tag. The above procedure, however, requires an additional operation flow f2' where f2' is a repeated execution flow. This additional flow f21 occurs because the decision concerning switching to the next instruction is made in phase-2 of the last operation flow of the present instruction, and at phase-2, the phase-1 of the next or repeated operation flow f2' has already started. With the system of FIG. 2, therefore, the operation speed of the whole apparatus tends to be decreased whenever a repeated execution instruction results in plural execution flows.
The present invention has been proposed to solve the above-mentioned wasted execution cycle problems inherent in conventional systems.